1. Field of the Invention
The invention relates to design methodologies for electrical systems, more in particular electrical circuits (especially digital circuits), to circuitry designed with said methodologies and to circuit parts, specially designed and incorporated within said digital circuits to enable operation of said circuits in accordance with the proposed concepts.
2. Description of the Related Art
Technology scaling has historically improved the performance of embedded systems, both in energy consumption and in speed. Scaling minimum feature sizes below 100 nm however, brings a host of problems, which cannot be completely solved at technology level. Back-end performance degradation, increased leakage currents and increased process variability are only a few examples. Process variability is probably the most important one because it has a direct negative impact on yield and it has a large impact on all the characteristics of the system, as described by H. Chang et al. in “The certainty of uncertainty: randomness in nanometer design”, Proc. of PATMOS, pp. 36-47, 2004.
Due to the stochastic nature of process variability, the only way to maximize the parametric system yield, i.e. the number of samples that meet the timing constraints, is either by incorporating corner-point analysis in the designs, or by run-time techniques which can measure the actual variability and adapt the operation of the system, because it is impossible to predict the impact of process variability on a system before the chip is processed.
Especially deep submicron (DSM) technologies, e.g. process technology nodes for 65 nm and beyond, suffer from large variability in integrated circuit (IC) parameters. These variations may be due to several reasons:                “process” differences between dies (inter-die variations).        “spatial” differences in processing for different parts of the die (intra-die variations). There is an increasing difficulty in controlling the uniformity of critical process parameters (e.g. doping levels) in the smaller devices, which makes the electrical properties of such scaled devices much less predictable than in the past.        “temporal” differences due to “degradation” processes. These include electromigration (which influences resistance R and partly capacitance C of lines), self-annealing of Cu (which influences resistance R of lines), stability of low-k dielectrics (which influences R/C of lines) and of high-k dielectrics (which influences threshold voltage Vt), hot electron trapping (which also influences threshold voltage Vt) and cross-talk (which causes “pseudo C” changes and noise). These temporal differences should be relatively slow and easy to “follow up” or monitor.        “temperature-related” differences due to strong variations in temperature T over time. Because of this, threshold voltage Vt and resistance R of lines are influenced. These temperature-related differences can vary quite fast (up to msec range) and hence are more difficult to monitor and calibrate.        
Memories are among the most variability sensitive components of a system. The reason is that most of the transistors in a memory are minimum-sized and are thus more prone to variability. Additionally some parts of the memories are analog blocks, whose operation and timing can be severely degraded by variability, as illustrated in FIG. 1, showing the impact of process variability on the energy/delay characteristics of a 1 kByte memory at the 65 nm technology node. The solid blocks on the bottom left indicate the simulated nominal performance assuming no process variability (squares for writing and triangles for reading). The other points are simulation results incorporating the impact of variability (+-signs for writing and ×-signs for reading). The energy consumption and delay of a memory designed using corner-point analysis is also shown (black circle).
In a target domain of multimedia applications, memories occupy the majority of the chip area even in current designs and contribute to the majority of the digital chip energy consumption. Therefore they are considered to be very important blocks for a system.
Solutions Offered in the Technical Background
Process variation has thus become a serious problem for continued technology scaling. It becomes harder and harder to deal with this at the technology and circuit levels only. Several proposed schemes are not even scalable to deep-submicron technologies because the body-bias effect will become very small.
If all of these effects have to be characterized at “design time”, and furthermore it has to be guaranteed that the design will still work under all possible conditions, the slack that will have to be introduced will become prohibitive in the deep-submicron era.
Maximizing parametric yield in memories via corner-point analysis and design will, by the size of the “clouds” due to process variability, lead to severe overheads in energy consumption and delay, as indicated in FIG. 1 (black circle). The reason is that the memory design will use over-sized circuits and conservative timing margins to improve the predictability of the memory behaviour by trading off performance.
Even when such so-called corner-point approach that leads to very worst-case nominal designs is substituted by a more stochastic analysis at design-time, as e.g. described by C. Visweswariah in “Death, taxes and failing chips”, Proc. 39th ACM/IEEE Design Automation Conf., New Orleans La., pp. 343-342, June 2002, the gain is relatively small compared to increased problem when scaling further.